Design and investigation of a dual source and U-shaped gate TFET with n buffer and SiGe pocket

Haiwu Xie,Hongxia Liu

doi:10.1063/5.0006510

Abstract

In this paper, we propose and simulate a novel structure of a double source and U-shaped gate tunnel field effect transistor (DS-UTFET) with an n buffer layer and n+ SiGe pocket. In order to reduce the OFF-state current, there is an n buffer layer under the n+ SiGe pocket in a sandwich stack; moreover, we use a source region overlap in both the vertical and lateral directions to enhance the electric field; as a result, considerable ON-state current and a high Ion/Ioff ratio are realized in the proposed structure. In our simulation, the DS-UTFET shows better performance than the UTFET, and the simulation results indicate that the ON-state currents of the DS-UTFET with and without an n buffer layer increase up to 2.52 × 10−4 A/μm and 2.47 × 10−4 A/μm, respectively, and the average subthreshold swing of the DS-UTFET with and without an n buffer layer is 35.0 mV/dec and 52.7 mV/dec, respectively, which ensures that the DS-UTFET has a fine analog and logic feature for applications; moreover, the maximum gm of the DS-UTFET with and without an n buffer layer is 519 µS/μm and 493 µS/μm at 1.4 V drain-to-source voltage (Vds). In addition, the RF performance of devices depends on the cut-off frequency (fT) and gain bandwidth (GBW), and the DS-UTFET with and without an n buffer layer could achieve a maximum fT of 25.7 GHz and 22.5 GHz, respectively. Meanwhile, the DS-UTFET with and without an n buffer layer could achieve a maximum GBW of 3.56 GHz and 3.06 GHz, respectively.

Highlights

As the feature size decreases in MOSFETs, VDD scaling of MOSFETs is no longer viable, a dramatic increase in the OFF-state current and severe short channel effects (SCE) cannot be avoided, and the limitation of 60 mV/dec subthreshold swing (SS) cannot be broken, so the continuous scaling of a conventional MOS device is extremely difficult in a nanoscale circuit
In order to overcome these issues, different types of structures have been investigated in recent years; among them, the tunnel field-effect transistor (TFET)1–14 is a selective candidate for future low power applications15–20 due to its process scalability and process compatibility with complementary MOS (CMOS), which employs the bandto-band tunneling (BTBT) mechanism rather than thermal electron emission, so it can break the limitation of 60 mV/dec,21,22 whereas low ON-state current is an inherent disadvantage in different planar TFETs because of a limited band-to-band tunneling rate and tunneling area
The proposed structure adopts allSi dual sources and has a stack in the source (p+ Si/n+ SiGe pocket/n+ Si buffer) region, wherein a SiGe n+ pocket (L-shaped) is inserted between the source and the channel region, which makes the BTBT occur in perpendicular direction and parallel direction simultaneously; that is to say, the point tunnel and linear tunnel coexist, and the linear tunnel dominates in the DS-UTFET; at the same time, an n buffer layer is introduced under the pocket in order to further reduce the OFF-state current

Summary

INTRODUCTION

As the feature size decreases in MOSFETs, VDD scaling of MOSFETs is no longer viable, a dramatic increase in the OFF-state current and severe short channel effects (SCE) cannot be avoided, and the limitation of 60 mV/dec subthreshold swing (SS) cannot be broken, so the continuous scaling of a conventional MOS device is extremely difficult in a nanoscale circuit. To obtain higher ON-state current and steeper SS, various novel device structures have been proposed, such as L-shaped TFETs, U-shaped TFETs, symmetric tunnel field-effect transistors (S-TFETs), covered source–channel tunnel field effect transistors (CSC-TFETs), heterojunction tunneling field-effect transistors with T-shaped gates (HTG-TFETs), and U-shaped channel with dual source TFETs (DUTFETs).. The DUTFET enhances the ON-state current of TFETs significantly on account of dual sources in its structure, while the OFF-. The Silvaco Atlas simulation results show that the DS-UTFET has high ON-state current and low OFF-state current compared with the UTFET and achieves a steep SS within a large gate voltage scope.

DEVICE STRUCTURES

SIMULATION AND DISCUSSION

CONCLUSION