Abstract
A Universal Asynchronous Receiver Transmitter (UART) is frequently used in conjunction with RS 232 standard, which sends parallel data through a serial line. The transmitter is essentially a special shift register that loads data in parallel and then shifts it out, bit by bit at a specific rate. The receiver, on the other hand, shifts in data bit by bit and then re-assembles the data. UART is implemented using FPGA by considering two Development and Education boards where each has a transceiver module. Bidirectional routing is established using RS 232 interface to communicate the two transceiver modules. This is designed and implemented using Quartus and Cyclone IV FPGA. The total power of the transceiver module using Cyclone IV is analyzed and compared with that of the transceiver implemented using different FPGAs.
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