Design and Implementation of the Scan Digital Display Based on FPGA

Abstract

The scan digital display has the function of receiving and processing digital signals. As an advanced display type, the digital display presents a trend of accelerating development. Because of shortage of the long development cycle and high price of the traditional display design, this paper designs a scan display with six-bit Nixie tubes to achieve dynamic refresh display based on FPGA. This design adopts EDA technology, using VHDL as the hardware description language and Quartus II as the development platform to construct the scan digital display, which consists of the DATA module, multi-channel data selection module and BCD decoding module. Finally, the correctness and effectiveness of the digital display is validated by the compilation and simulation of the program downloaded from the programmable logic devices. This scan digital display has the characteristics of high speed, low power consumption and low cost which can be widely used in the market. The digital display is a display with the function of receiving and processing digital signals, which is widely used in various fields and brings much convenience to people's life(1). The system of scan digital display discards the old work way of putting monitoring and calculation together and the way of setting status. At present, the design platform of the scan digital display is mainly conducted on single chip, while in this paper, the design is based on FPGA. FPGA is referred to the field programmable gate array. The design of FPGA device is flexible and convenient, which can be programmed more than once with the characteristics of high speed, low power consumption and low cost. Using FPGA to develop the digital system can significantly shorten the design time, reduce the number of peripheral circuit and development costs, and improve the reliability of the system.Therefore, realizing the digital scan display has an important realistic significance.