Abstract

The ATLAS detector has been designed for operation at CERN's Large Hadron Collider. ATLAS includes a complex system of liquid argoncalorimeters. The electronics for amplifying, shaping, sampling, pipelining,and digitizing the calorimeter signals is implemented on the Front End Boards (FEBs). This paper describes the design, implementation and production of the FEBs and presents measurement results from testing performed at several stages during the production process.

Highlights

  • ATLAS [1] is a large general-purpose detector designed for operation at the Large Hadron Collider (LHC) at CERN

  • The electronic readout of the ATLAS liquid argon (LAr) calorimeters is divided into a Front End (FE) system of boards mounted in custom crates directly on the cryostat feedthroughs, and a Back End (BE) system of VME-based boards located in an off-detector underground counting house

  • Instead of the plug-in preamp hybrids used for the rest of the LAr subsystems, the hadronic endcap (HEC) Front End Boards (FEBs) are equipped with plug-in “HEC preshapers” [16] that are designed to be pin-to-pin compatible with the preamp

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Summary

Introduction

ATLAS [1] is a large general-purpose detector designed for operation at the Large Hadron Collider (LHC) at CERN. The LAr calorimeters include the electromagnetic barrel (EMB) calorimeter, which is housed in the central cryostat and provides coverage for pseudorapidities |η| < 1.5. The ranges of larger pseudorapidity are covered by endcap calorimeter (EC) systems, housed in separate endcap cryostats. The electronic readout of the ATLAS LAr calorimeters is divided into a Front End (FE) system of boards mounted in custom crates directly on the cryostat feedthroughs, and a Back End (BE) system of VME-based boards located in an off-detector underground counting house. The FE system includes Front End Boards (FEB), which perform the readout and digitization of the calorimeter. The overall system performance of the ATLAS LAr readout electronics will be documented in a subsequent publication

FEB specifications
Overview of the FEB architecture
19 VREG 7 voltages
Preamplifiers
Hadronic Endcap Preshapers
Shaper
SCA analog pipeline
Digitization and Gain Selection
SCA Controller and FEB Digital Control
SCA control and Address Bus
Output optical link
FEB output data format
Level 1 Trigger Summing
10. FEB Control Interfaces
10.1 Trigger and Timing Control
10.2 Clock distribution
10.3 Configuration and slow control
11. FEB power distribution and monitoring
12. FEB layout and topology
13. FEB production
14. FEB testing
14.1 Initial test and highly accelerated stress screening
14.2 Digital test
14.3 Analog test
15. Performance of the FEB
Findings
16. Summary
Full Text
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