Design and Implementation of the Combinational Circuits Testing using Accumulator based BIST to Reduce Delay, Power Consumption and Area

Abstract

Background: In Current VLSI circuits, e.g., Modules like accumulators, Arithmetic Logic Units (ALUs) are present generally in information line structure or discrete signal Processing chips. ABIST has a basic idea that is used by accumulators for built-in testing and its generated test patterns show the hardware overhead degradation and decreased circuit speed. Method: In the present system this paper use a scheme which holds a generation of test patterns and is compared with previously proposed scheme. The test patterns created by accumulator proves that it takes input produced by a constant pattern holding an acceptable pseudo random individuality, if a proper input pattern is selected. Weighed pseudorandom BIST schemes were utilized to bring down the vector number in BIST applications. Findings: For the generation of test patterns, we use a group which has 0, 1 and 0.5 weights and this group is an impartial group and this use will lower the time needed for testing and also reduces power used. In the above work, digital circuits such as G27 Bench mark and SISO are, accumulator based BIST. Finally, the synthesis results of these circuits are compared with normal BIST. It was found that the circuit as low delay using accumulator based BIST.