Design and implementation of shared memory with adjustable priority

Abstract

With the rapid increase of the computing performance of application systems, multi-core architecture technology has been widely used in modern processor, and the "memory wall" has spawned the design requirements for efficient on-chip shared memory. For shared memory, access delay, bandwidth, and capacity are the three important performance evaluation indicators. This paper designs an on-chip shared memory with adjustable access priority for a multi-core processor, which is visible to the programmer and able to support multiple accesses from n (configurable) groups of host ports. Its memory capacity can be flexibly configured to 2, 4, 6, 8 and 16MB, and it has an internal arbitration system that could dynamically adjusts the priority of the host. This design effectively improves the bandwidth utilization rate when multiple hosts access the shared memory, and solves the problem of "starvation" or "stroke to death" that may occur when hosts of different priority levels access the shared memory in parallel.