Abstract

In this paper, a three-dimensional heterogenous-integrated (3DHI) wafer-level packaging (WLP) process is proposed, and a radio frequency (RF) front-end module with two independent ultra-high frequency (UHF) receiving channels are designed and implemented, which covers 400 MHz–600 MHz and 2050 MHz–2200 MHz respectively for unmanned aerial vehicle (UAV) applications. The module is formed by wafer-to-wafer (W2W) bonding of two high-resistivity silicon (HR-Si) interposers with embedded bare dies and through silicon via (TSV) interconnections. Double-sided deep reactive ion etching (DRIE) and conformal electroplating process are introduced to realize the high-aspect-ratio TSV connection within 290 µm-thick cap interposer. Co-plane waveguide (CPW) transmission lines are fabricated as the process control monitor (PCM), the measured insertion loss of which is less than 0.18 dB/mm at 35 GHz. The designed RF front-end module is fabricated and measured. The measured return loss and gain of each RF channel is better than 13 dB and 21 dB, and the noise figure is less than 1.5 dB. In order to evaluate the capability of the 3DHI process for multi-layer interposers, the module is re-designed and fabricated with four stacked high-resistivity silicon interposers. After W2W bonding of two pairs of interposers and wafer slicing, chip-to chip (C2C) bonding is applied to form a four-layer module with operable temperature gradient.

Highlights

  • The development of a highly integrated and high-performance radio frequency (RF) module based on silicon technologies in recent decades has attracted more and more attention in modern communication systems

  • These experimental results indicate that great RF performance is obtained by the provided interposer process, and the high-resistivity silicon (HR-Si) interposer has little contamination and few defects which remains similar to high resistivity RF behavior under different bias voltage

  • The two low noise amplifiers (LNAs), two SWs, and two decoupling chip capacitors are mounted on the GND pad of RDL3 layer, which are well grounded by through silicon via (TSV) arrays

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Summary

Introduction

The development of a highly integrated and high-performance RF module based on silicon technologies in recent decades has attracted more and more attention in modern communication systems. Reference [1] introduces several multi-layer substrates which are commonly chosen for microwave or millimeter-wave 3D packaging process, like high temperature co-fired ceramic (HTCC) [2,3], low temperature co-fired ceramic (LTCC) [4,5,6], and organic substrate [7,8]. Vertically stacked HR-Si interposers with embedded chips have more advantages in flexible heterogenous integrations than in the traditional heterostructure semiconductor process [12,13]. HR-Si interposers with embedded chips and through silicon via (TSV) interconnections This multi-layer wafer is diced and measured; after that the cap wafer and bottom wafer with different type of TSVs are bonded.

Process Flow of the 3DHI WLP
Process of the Bottom Interposer Wafer
Process of the Cap Interposer Wafer
Chip Embedding with W2W Bonding
Assemblies Stacking with C2C Bonding
Process Verification by PCM Test
System Architecture of the RF Module
Simulation of the Key Structures
Measured Result
The Design of Four Layers Stacked RF Module
Conclusions
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