Design and implementation of programmable read only memory using reversible decoder on FPGA

Abstract

Reversible logic is the emerging field for research in present era. The aim of this paper is to design and synthesize a Programmable Read Only Memory (PROM) using a reversible decoder which is designed using reversible logic with minimum quantum cost. The PROM is a Programmable Logic device which consists of fixed AND Gates and programmable OR gates array. Fixed AND gates can be termed as a decoder. PROM finds its applications in cell phones, RFID tags, video game consoles, medical devices, computers and other electronic devices. An n input and k output Boolean function f (a1, a2, a3, ….an) (referred as (n, k)) is said to be logically reversible if and only if, the number of inputs are equal to the number of outputs i.e., ‘n’ equals ‘k’ and the input pattern uniquely maps the output pattern. The reversible logic must run both forward and backward as well such that the inputs can also be retrieved from outputs. There are many reversible logic gates in literature like NOT gate, Feynman Gate (CNOT gate), Double Feynman Gate, Peres Gate, TR gate, Seynman Gate and many more. Fan-out and Feed-back are not allowed in Logical Reversibility. To overcome the Fan out limitation, the signals from required output lines are duplicated to desired lines using additional reversible combinational circuits. Reversible Logic owns its applications in various fields which include Quantum Computing, Optical Computing, Nano-technology, Computer Graphics, low power VLSI etc., Reversible logic is gaining its own importance in recent years largely due to its property of low power consumption and low heat dissipation. In this paper, the Programmable Read Only Memory (PROM) using reversible decoder which has less heat dissipation and low power consumption is proposed. The designed circuit is analyzed in terms of quantum cost, garbage outputs and number of gates. The Circuit has been designed and simulated using Xilinx software and implemented on FPGA SPARTAN — 3E.