DESIGN AND IMPLEMENTATION OF PARTIALLY RECONFIGURABLE FP-AU

Abstract

In this paper we present the partial reconfiguration of floating point arithmetic unit that improves the area occupied by floating point arithmetic unit and also makes this unit flexible to operate in a rapidly changing environment. The hardware resources occupied by this unit have been reduced through time-sharing them between modules. Since the FP-AU occupies a significant amount of silicon area in any application due to wide dynamic range, our proposed design shows a very efficient area reduction technique for FP-AU. Partial reconfiguration is the ability of certain Field Programmable Gate Arrays (FPGAs) to reconfigure only selected portions of their programmable hardware while other portions continue to operate undisturbed. A FPGA can be partially reconfigured using a partial bitstream. We can use such a partial bitstream to change the structure of one part of an FPGA design as the rest of the device continues to operate and this reduces the reconfiguration time. The floating point arithmetic unit is modeled in VHDL and synthesized with Xilinx ISE tools. The floating point arithmetic modules are designed for Virtex-2 Pro XC2VP50 FPGA.