Design and implementation of MPSoC single chip with butterfly network

Abstract

Multiprocessor System on Chip (MPSoC) are increasingly considered as the post promising solution for complex embedded applications. The most significant MPSoC design challenge comes from interconnect infrastructure. Network-on-Chip (NoC) with multiple constraints to be satisfied is a promising solution for these challenges. It has been shown that infrastructure topology; routing and switching schemes have great effects on overall interconnect performance under different synthesis and real life traffic patterns. In this paper, we report the design and single FPGA chip implementation of an 8-node butterfly network based on MPSoC. We analyze the performance of this MPSoC on a radix-2 Fast Fourier Transform whereas the FFT algorithm is parallel programmed and it uses our NoC as a communication environment. Additionally, an exploration is done in two dimensions the number of processors used in parallelism process and the input dataset size of the FFT.