Abstract

In the present design algorithms, the speed of the multipliers is limited by the speed of the adders utilised. This work is dedicated for the design of a 16-bit multiplier which is proposed using a vedic sutra named Urdhva Tiryagbhyam from Vedic Mathematics. The 16-bit multiplier is realized using a 8-bit multiplier which inturn realized by a 4-bit multiplier and so on. Modified Ripple Carry Adders[7] are used to built the multiplier circuit. In the proposed design we have reduced the number of logic levels, thus reducing the logic delay. Also the area utilized is reduced by the design algorithm. Simulation of the architecture is performed using Xilinx ISIM and synthesized using Xilinx XST. The implementation is done in FPGA Spartan Kit.

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