Design and implementation of low power Advanced Encryption Standard S-Box using pass transistor XOR-AND logic

Abstract

Advanced Encryption Standard (AES) is the one of the successful algorithm in the cryptography. AES S-Box with minimal power consumption gives a typical challenge in today's research environment. In AES, S-Box consume more power when compare to the other AES operation. S-Box is implemented using the composite field which has the different arithmetic properties. In S-box, Algebraic Normal Form (ANF) is used to convert the composite field AES S-Box into the logic expression. Expressions involved in s-box are optimized by using pass transistor XOR-AND gates which leads to solve the complexity of the composite field pipelining architecture like power, area. This helps to reduce the dynamic power consumption. The design is implemented using the cadence Schematic Editor. The proposed methodology gives the low power as 3.996nW.