Design and Implementation of Low Energy Wireless Network Nodes Based on Hardware Compression Acceleration

Abstract

Background: With the fast development of information, the information data is increasing in geometric multiples, and the speed of information transmission and storage space are required to be higher. Objective: In order to reduce the use of storage space and further improve the transmission efficiency of data, data need to be compressed. In the process of data compression, it is very important to ensure the lossless nature of data, and lossless data compression algorithms appear. The gradual optimization design of the algorithm can often achieve the energy-saving optimization of data compression. Similarly, the effect of energy saving can also be obtained by improving the hardware structure of node. Methods: In this paper, a new structure is designed for sensor node, which adopts hardware acceleration, and the data compression module is separated from the node microprocessor. Result: On the basis of the ASIC design of the algorithm, by introducing hardware acceleration, the energy consumption of the compressed data was successfully reduced, and the proportion of energy consumption and compression time saved by the general-purpose processor was as high as 98.4 % and 95.8 %, respectively. It greatly reduces the compression time and energy consumption.