Design and implementation of high-speed symmetric crossbar schedulers

Abstract

Crossbar architectures are widely used to implement high-performance network switches and routers. A crossbar switch can transfer cells between multiple ports simultaneously by closing multiple cross points. This crossbar configuration must be determined by an intelligent centralized scheduler that can ensure fairness and high utilization. In this paper, we describe the design and implementation of two symmetric scheduling algorithms for configuring crossbars in input-queued switches that support virtual output queueing. Our target is a fast packet switch that can support 32 ports, each operating at 20 Gbps. Using a 0.35 /spl mu/m CMOS process, the faster of the two schedulers is capable of configuring a 32/spl times/32 crossbar once every 12.61 ns. Our scheduler designs are based on a two-dimensional ripple carry arbiter architecture. To ensure fairness, both architectures support a round robin priority rotation scheme. Based on network simulations, we show that our arbiter designs can achieve near optimal system performance.