Design and Implementation of High-Speed Low-Power Carry Select Adder

Abstract

In VLSI, performance of processors and systems is mainly influenced by adders; therefore, designing an adder optimizing all design constraints such as speed, power, and area has become a biggest challenge where more research is happening. In this paper, four types of adders are designed and compared. Ripple carry adder (RCA) comparatively occupies lesser area with more delay than carry look ahead adder (CLA) which has less delay. So, carry select adder (CSA) is designed which is a trade-off between RCA and CLA. Conventional CSA is usually designed using dual RCAs. In this paper, CSA is presented using Brent Kung adder (BK) which optimizes the design constraints like speed, area, and power compared to all other adders mentioned. RCA, CLA, regular linear Brunt Kung carry select adder (RL BKCSA), and modified square root (MSQRT) Brent Kung CSA are designed in Xilinx. Their performances are compared in view of different design constraints to implement better adder on FPGA and used in FFT algorithm, which is a major application in DSP processors used for filters to reduce the computations than using DFT.