Design and implementation of high-speed, low-area switch debouncer ASIC for deep submicron technology

Abstract

Mechanical switching Contacts tend to make and break connections for a finite time before settling down to a stable state. This settling time or bouncing activity becomes havoc in digital circuits because within the settling time the circuit can see multiple transitions as the switch contacts bounce between make or break conditions. Not only in digital circuits, switching noise becomes a major limitation in mixed signal SoC integration as well. Switch debouncer circuit is the one which takes an input signal from a bouncing contact and generates a clean digital output for high speed circuits. The switch debouncer(SD) circuit will not pass the signal to the output till the predetermined period of time until the switch bouncing settles down. In this way, the circuit will respond to only one pulse generation performed by the depressing of the switch and not several state transitions caused by contact bouncing. In this paper an ASIC is designed for eliminating these switch bouncers. The basic building blocks involved in the design of this debouncer circuit are D Flip flop, input and output pads and XOR gates. In this proposed design, DFF and XOR gates are implemented using pass transistors and transmission gates which increases the speed and reduces the area and power consumption. This design has been successfully implemented and tested with a high speed serial adder. The schematics and layout are generated using Tanner EDA and simulations are performed using 90nm technology file. The supporting results and comparisons are provided in the paper.