Abstract
The Fano sequential decoding algorithm can provide lower hardware complexity when compared with the Viterbi algorithm, but it has variable computational delay similar to the other sequential decoding algorithms and the delay is significantly high at low SNR values. Bidirectional decoding technique can be applied to reduce the delay, but hardware resources consumed must be considered. In this paper, we present the design and implementation of a recently proposed bidirectional Fano decoding algorithm. We show that when implemented on an FPGA, the bidirectional Fano decoder can work faster than two parallel unidirectional Fano decoders while consuming the same hardware resources.
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