Abstract
In this chapter, the main aspects of the design of baseband hardware modules are addressed. Special attention is given to word-length optimization, implementation, and validation tasks. As a case study, the design of an equalizer for a 4G MIMO receiver is addressed. The equalizer is part of a communication system able to handle up to 32 users and provide transmission bit-rates up to 125 Mbps. The word-length optimization process will be explained first, as well as techniques to reduce computation times. Then, the case study will be presented and analyzed, and the different tasks and tools required for its implementation will be explained. FPGAs are selected as the target implementation technology due to their interest from the DSP community.
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