Design and implementation of hardware-efficient modified Rao–Nam scheme with high security for wireless sensor networks

Abstract

This paper presents the design and implementation of a crypto channel coder with very low hardware complexity and high security for securing communication in resource-constrained applications such as Wireless Sensor Networks (WSNs). The integrated secure channel coder system is proposed as a modification of the Rao–Nam (RN) scheme by embedding security in a structured Low-Density Parity-Check (LDPC) code. A novel stream ciphering method based on the Linear Feedback Shift Register (LFSR) with high throughput is incorporated to generate random error vectors, so that a large number of vectors with very good cryptographic properties can be made available with simple hardware. An efficient design method to vary the encryption matrix and the intentional error vector with each message block provides high degrees of freedom for an intended receiver without compromising hardware simplicity. Prototypes of the proposed encoder architecture with both (28, 14) and (248, 124) Quasi-Cyclic (QC) LDPC codes have been implemented on Xilinx Field Programmable Gate Array (FPGA) Spartan 3E kit using Very High Speed Integrated Circuit Description Language (VHDL). Analytical and synthesis results show that this scheme is highly suitable for resource-constrained applications such as wireless sensor networks due to its low hardware complexity and high security.