Abstract
This paper demonstrates the design and implementation of Equiripple linearphase FIR high pass filter. The filter is modeled using Simulink in Xilinx System Generator. The filter Coefficients are generated with the help of FDA tools, the SysGen tool is used for RTL code generation. Further the model is used as a filter block to interface with ADC/DAC block in VHDL. The design has been prototyped on Spartan-3 DSP protoboard XC3S500fg320 using Integrated Synthesis Environment (ISE) 13.1 tools all in one design suit from Xilinx. Finally the filter is tested by using an audio signal as input and the output is observed in CRO & speaker both.
Highlights
The design of FIR filter using Windows methods leads to good performance filters
Creation of Simulink model The Xilinx System Generator for DSP [5,6,7] is a system level modeling and design tool that facilitates for Xilinx FPGA design and has the ability to work at a higher level of abstraction
The System Generator integrates itself with Simulink and FPGA designs are captured by using the Xilinx specific Blockset
Summary
The design of FIR filter using Windows methods leads to good performance filters. sometimes there is a need to design an FIR filter that performs well but it is optimal. Optimization is the ability to specify a maximum error on each band of interest This error is expressed as the absolute difference between the ideal or the desired frequency response and the actual or resulting frequency response. In this method that “spreads out” the error over the passband in an Equiripple fashion, such that the maximum error is the same at several points and can be made very small. The Equiripple algorithm applies to a number of FIR design instances
Sign-in/Register to view highlights & summary Sign-in/Register to access full text options 
Free) 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a call
