Design and Implementation of Efficient Reed-Solomon Decoder for Intelligent Home Networking

Abstract

Intelligent home concept is the integration of different services within a home by using a common communication system. Error correction coding is being used on an almost routine basis in most communication systems including intelligent home networking. In addition, critical protocol management information requires high fidelity forward error correction (FEC) coding to ensure that the protocol functions correctly in the worst case situations. A powerful technique in the worst case situations is a Reed-Solomon (RS) code. With this technique, one achieves a high level of performance by trading an increase in overall block length for a reduction in hardware complexity. This paper concerns the design and implementation of RS codec for intelligent home networking. The 3 symbol error correcting RS codec is developed on field programmable gate array (FPGA) chips using very high speed integrated circuit hardware description language (VHDL). The logic functions are confirmed by VHDL simulator tool. The circuits are generated by the synthesis tool. Two FPGA chips are required and the FPGA utilization is 70% and 40%, respectively.