Design and Implementation of Efficient DA Architecture for LeGall 5/3 DWT

Abstract

In recent years, wavelet-based image and video processing has gained an increasing importance in multimedia applications. In this paper, we have designed and implemented a hardware-efficient lossless LeGall 5/3 Discrete Wavelet Transform (DWT) using the Distributed Arithmetic (DA) architecture. The DA based architecture exploits the computational similarities within the intermediate results of the co-efficient module and only uses adders and shift registers, to achieve low complexity architecture. In our proposed implementation, the DWT coeffi-cients are distributed by selective evaluation of input and output with the preferred precession of the coefficients. The DWT is implemented using HDL (Hardware Description Language) on an Altera DE1 Cyclon II FPGA (Field Programmable Gate Array) device. A hardware comparison shows savings exceeds 75% compared to the direct filter, and 22% in comparison to the other general purpose and optimized DWT architectures. The proposed solution is high performance, low-power and greatly alleviates the real-time transmission and compression of high-fidelity video over bandwidth-limited channels.