Design and Implementation of DSP-based Three-level Simplified SPWM Modulation Method

Abstract

The traditional three-level sinusoidal pulse width modulation (SPWM) requires two carriers to be compared with the modulating waveform to get the duty cycle, which can not be realized in a single-core DSP chip with high requirements. This paper proposes a three-level single-carrier SPWM waveform implementation method that does not increase the hardware cost. The scheme is based on the DSP28335 chip, using the DSP chip’s increment/decrement counting method, the comparison counter, and the DSP interrupts to compare the carrier waveform with the modulating waveform and get the PWM drive signals with different duty cycles. Simulation results show that compared with the traditional three-level SPWM algorithm, the proposed three-level simplified SPWM modulation not only controls the hardware cost, but also optimizes the bias of the intermediate capacitor voltage on the DC bus side, which reduces the harmonic distortion of the grid, shortens the time for the DC output voltage to reach the steady state, and verifies the effectiveness of the proposed modulation method.