Design and Implementation of Decision-Tree (DT) Online Training Hardware Using Divider-Free GI Calculation and Speeding-Up Double-Root Classifier

Abstract

This paper proposes a total solution in ASIC chip hardware implementation, fulfilling decision-tree (DT) online training and classification missions. We also develop three effective design techniques, including divider-free resister-in-parallel Gini Impurity calculation (DR-GIC), adaptive means with updated learning function (AM-ULF), and speeding-up classifier with double-root tree (SC-DRT). In the ASIC chip implementation with TSMC 40-nm multi-Vt CMOS process, the chip layout is well-verified and only has a total core area of 0.803 mm2. The maximum operating frequency is 429 MHz, dissipating average power of 73.7 mW. Regarding online training, it supports a maximum training size of 10.1KB data on chip. Accordingly, the worst-case training latency is only 9.98ms for dealing with 1024 data elements. For classification, the decision throughput is up to 4.29 GBps – 8.58 GBps. After being verified with various datasets for different applications, the ASIC chip with superior design performance offers a solid hardware implementation, realizing a total DT-based procedure from online training to classification.