Design and implementation of boundary scan testing of core logic on FPGA

Abstract

Boundary Scan technique is one of the strategies of testing Integrated Circuits (ICs), wiring connections on printed circuit boards or sub-modules. The boundary scan circuitry is inserted at the inputs of ICs and testing is done by feeding test patterns. To overcome the drawbacks of primitive testing methods like in-circuit, functional testing techniques, a newer boundary scan technique is adopted in the proposed paper which reduces the testing time and cost. There is a need for low cost PCB test technology, which allows the miniaturization of PCBs with simple design rules [1]. The test patterns are stored in the input data register and are fed as inputs to the boundary scan cells. The test patterns are also fed to the core logic circuit that is being tested. The core part of the technique includes the design of main module called tap controller. JTAG TAP controllers have become a deliverance and control mechanism for Design for Test [2]. Its output is stored in the register and compared with the known value to conclude whether the IC is functioning properly or not. The effectiveness of this design is measured in terms of parameters such as area, power and the speed.