Design and Implementation of Argo NI-NoC Micro-architecture for MPSoC Using GALS Architecture

Abstract

As the networks on chips is used for designing the multi-processor system on chips, this platform have been typically guaranteed for hard real time property, and for the use of shared resources in a network. The service guarantees has to be provided by the network with respect to bandwidth and latency for a different communications flow. Thus message passing communications between the processor cores are implemented for the network on chip. The TDM is used for controlling the communications over the structures of router, links and network interface. The two main contribution of area efficient are (i) The TDM schedule with combined asynchronous router and (ii) The micro-architecture of NIs. In concert with the design resulted with the transforming the data in a pipelined manner which means transmitting the data from the local memory of send core to the local memory of the receive core, without using any dynamic attributions, buffering and local synchronization. The router also uses the two phase bundled data hand shake latches based on the mousetrap latch controller and it is extended with the gated mechanism for reducing the energy consumption. Network interface is used for integrating the DMA and the TDM functionalities. The dual ported local memory is used for avoiding buffering, flow controls and synchronization. Thus obtained result is verified with respect to area, power and gates.