Design and Implementation of an On-Chip Test Generation Scheme Based on Reconfigurable Run-Time Programmable and Multiple Twisted-Ring Counters

Abstract

Built-in-self-test (BIST) has emerged as a very effective solution to VLSI testing problems. Related work based on single fixed-order twisted-ring-counter design requires longer testing time to achieve high fault coverage and large storage space to store the seeds and the control data. By using multiple programmable twisted-ring-counters (PTRC), a considerable reduction in test application cycles were achieved. In this paper, an on-chip test generation scheme based on reconfigurable run-time programmable multiple twisted-ring-counters is proposed to generate more number of different test patterns based on the requirements. The design was modeled in VHDL and simulated and synthesized using Xilinx ISE 14.2.