Design and Implementation of an Efficient VLSI Architecture for 10T Full Adder Used in Ultra Low Power Applications

Abstract

Full adder is an important digital design for development of many digital systems. For an efficient digital system design, an area efficient and high-speed full adder is very much needed. This full adder is very much needed for ultra low power applications. In this paper, an efficient VLSI Architecture is proposed for the 10T full adder. The proposed VLSI architecture consumes less power, less area, and operates at higher speed. This VLSI architecture has been implemented using 180 nm technology using Generic Process Design Kit (GPDK) with the help of Cadence Design suite. The VLSI architecture can be synthesised with reduction in power and high speed. The proposed VLSI architecture has been compared with different full adder cells. The proposed full adder architecture performance can be analyzed by using parameters such as energy, propagation delay, leakage power, and total power.