Design and Implementation of an Analog Constant Power Load for Studying Cascaded Converters

Abstract

One of the major issues in multi-converter power electronic systems is the constant power load (CPL) behavior of the tightly regulated converters. In order to have better system performance, output of the converters should be tightly regulated. DC/DC converters when tightly regulated act as constant power loads. The current through a constant power load increases/decreases when the voltage across it decreases/increases, respectively. As a result, CPLs have negative impedance characteristics. This is a destabilizing effect known as negative impedance instability. In order to analyze cascaded DC/DC converters in multi-converter systems, an analog constant power load (A-CPL) that has a fast time response is developed and presented in this paper. It can be used as an ideal CPL for studying the mentioned issue in the laboratory. Since it is analog, the proposed A-CPL separates the problem of sub-harmonic production from the problem of negative impedance instability for research purposes. By changing the position of a manual switch, the implemented A-CPL can also operate as an adjustable power resistor or a current source for the laboratory experiments. The experimental results showing the performance of the A-CPL are also presented