Design and implementation of a novel low complexity symmetric orthogonal wavelet filter‐bank

Abstract

The design of wavelet filter-bank in real continuum domain demands infinite precision to achieve perfect reconstruction (PR). The computations with irrational coefficients in orthogonal filters require a large amount of hardware that result in increased power dissipation, huge memory requirements and reduction in speed of operation. This paper presents a new approach to obtain a complete dyadic (low complexity) 6-tap orthogonal symmetric wavelet filter-bank (FB) with near perfect reconstruction. This is achieved by slightly altering the PR conditions to make orthogonal filters symmetric and to obtain complete dyadic filter coefficients. The proposed wavelet FB has reduced dynamic power dissipation and significantly reduced adder and shifter count. The VLSI architecture of the proposed FB is designed and implemented on Kintex-7 FPGA. The architectural design is carried out using Verilog and functional simulation and synthesis are executed using Vivado 2016.4 software. The proposed FB dissipates 114mW dynamic power and requires only 5 adders and 3 shifters. The effectiveness of the proposed wavelet is verified in three different applications namely image compression, iris recognition system and orthogonal frequency division multiplexing (OFDM). The proposed wavelet FB gives comparable performance in image compression and attains superior performance in iris recognition system (feature extraction) and OFDM.