Design and implementation of a low-power 1V, 77.26µW 6-bit SAR ADC in Cadence 90nm CMOS process for biomedical application

Abstract

A micro-electronic system which deals with mixed signal circuits, requires both analog-to-digital converter (A/D) and digital-to-analog converter (D/A). In this project, we focus on wireless biomedical implantable devices where a highperformance ADC interfacing with bio-sensors, pacemaker or many other devices for health caring system is needed to communicate with human body. An extremely high speed is not necessary for such application, but power consumption is a seriously concerned issue. In this paper, we describe a low-power and medium-speed successive approximation register (SAR) ADC. The 6-bit ADC has been designed in 90nm CMOS process and is supplied with 1V. The key segments are a sample and hold (S/H) circuit, an analog comparator, a 6-bit SAR logic unit, which emulates the binary search logic of array and a 6-bit D/A converter. The simulation results show that the circuit consumes 77.26µW with the sampling frequency of up to 1MHz, zero offset, SQNR of 37.34 dB and ENOB of 5.91.