Design and Implementation of a High-Performance and High-Speed Architecture for Wideband Spectrum Sensing in Cognitive Radio Networks

Abstract

One of the key functions of the cognitive radio (CR) is to detect free bandwidths in a radio frequency spectrum. High-speed and energy-inefficient analog-to-digital converters (ADCs) are generally employed for spectrum sensing in sideband signals. The high-rate ADCs provide a large volume of raw data for digital signal processing blocks, resulting in complex and energy-inefficient circuits and hardware resources in digital blocks. In many applications, the frequency spectrum is sparsely occupied by different users. In other words, only a few active frequency bands exist at the same time. This feature enables the CR application to employ sub-sampling approaches in order to design a system with a significant reduction in cost and power consumption and improvement in processing speed. This paper presents a novel real-valued sparse spread spectrum sensing algorithm (CR4S) based on a sub-sampling solution, which uses the sparsity of the frequency spectrum and the real-valued properties of the RF signal to detect free bandwidths with minimum computations. The CR4S algorithm utilizes techniques such as sparse fast Fourier transform, real-valued FFT, and collaborative spectrum sensing to improve spectrum sensing in the CR. The analysis and simulation of the proposed algorithm confirm it achieves above 95% detection performance. Furthermore, a high-throughput architecture with minimum resource utilization is suggested to implement the CR4S algorithm in the field-programmable gate array (FPGA). When implementing the CR4S algorithm, we reached 25% speed improvement and 30% increase in FPGA recourse utilization efficiency, in comparison with a similar study in the literature. The capabilities of the CR4S algorithm in performance enhancement and low hardware resource utilization are an emerging approach, which would be fascinating in portable CR devices.