Design and implementation of a 1–5 GHz UWB low noise amplifier in 0.18 μm CMOS

Abstract

This paper presents a compact two-stage ultra-wideband low-noise amplifier (LNA). A common-gate topology is adopted for the input stage to achieve wideband input matching, while a cascode stage is used as the second stage to provide power gain at high frequencies. A low power consumption and a small chip area are obtained by optimizing the performance of the LNA with tight constraint on biasing current and reducing the number of inductors to two. The LNA has been fabricated in a standard 0.18 μm CMOS technology for experimental verification. The LNA achieves a power gain of 11---13.7 dB and a noise figure of 5.0---6.5 dB in the frequency band 1-5 GHz. The measured third order (two-tone) input intercept point (IIP3) is ?9.8 dBm at 4 GHz. The LNA consumes 9 mW with a 1.8 V supply, and it occupies an area of 0.78 mm2.