Design and Implementation of 8 Bit Successive Approximation ADC at 1MHZ

Abstract

Successive Approximation Analog to Digital converters (ADCs) are very popular for reasonably quick conversion time and good resolution yet moderate circuit complexity. This thesis describes the design and implementation of a Successive Approximation ADC with 8-bit resolution at lMHz speed in 0.5 um CMOS technology. Design, architecture, methodology and performance of the proposed ADC are presented. The main features of the Successive Approximation (SAR) ADC architecture designed are very low power dissipation and small chip area because of the comparatively simple circuit implementation. The internal Digital to Analog Converter (DAC) is the most important block of the SAR ADC. Division of Charge implementation was used to realize the DAC to minimize the short-comings of the conventional charge-redistribution implementation. The SAR ADC was realized using Switched Capacitor circuitry. The hardware implementation of the schematic was done in MAGIC and the functionality of the ADC was tested in HSPICE. A test chip was fabricated and received for verification of the simulation results.