Design and Implementation of 64-bit Carry Lookahead Adders Using Fixed and Variable Stage Structure

Abstract

Adders are basic integral part of arithmetic circuits. The adders have been realized with two styles: fixed stage and variable stage size. This paper presents the correlation investigation of execution examination of 64-bit Carry Lookahead Adders utilizing conventional and hierarchical structure styles with fixed stages and variable stages. We utilize different diverse parameter to evaluate conventional carry lookahead adder (CLA) and hierarchical carry lookahead adder (HCLA) and variable stage carry lookahead adder. Our outline is actualized into Zedboard Xilinx Zynq XC7Z020-1CLG484. Our intrigued of investigation are delay, area, and power. In this paper we show conventional CLA required small area using radix-2, while in hierarchical CLA delay is diminished to a great extent. Furthermore, we demonstrated variable stages CLA would be able to tradeoff between the area, delay and power.