Design and Implementation of 32-Bit MIPS RISC Processor with Flexible 5-Stage Pipelining and Dynamic Thermal Control

Abstract

The main aim of this design is design a 5-stage flexible pipelined 32-bit RISC-V processor using system Verilog including it Dynamic thermal management technique. This Design is be based on MIPS instruction set architecture(ISA) in which stages of pipeline include Instruction fetch, Instruction Decode, Execute, Memory access, Write back. The RISC[Reduced Instruction set Computed] compared to CISC[Complex instruction set computer] executes instruction in one clock and instructions are always uniformly lengthen and fixed instruction format based opcode. Hence RISC is preferable more used for less complex tasks and low power designs. Based on the literature the proposed design brings significant improvements in simulation speeds due to flexible pipeline technique and low power consumption is achieved. The Primary desire of this paper is to simulate and synthesize the design by perform basic ALU operations and provide desired outputs.