Design and hazard solving of five-stage pipeline RISC-V processor structure

Abstract

Benefiting from its late arrival, the RISC-V architecture capitalizes on the maturity of computer architecture technology achieved through years of development. This allows the RISC-V design to sidestep issues that have been exhaustively examined during the evolution of computer architecture over time. Adhering to a specific sequence for executing instructions with a CPU results in extended processing durations. However, in a pipelined architecture, the execution of one instruction doesn't disrupt the synchronized progression of other instructions. The introduction of a pipeline structure can improve processor speed, performance, throughput, and so on. In this paper, the pipeline structure is divided into five stages: fetch, decode, execute, memory and write back. It uses registers to solve the possible hazards of pipelining. The central processing unit employs the RISC-V RV32I foundational integer instruction set architecture. This paper used Verilog language to design, and Vivado simulation environment to simulate the design. The pipeline structure is simulated successfully, including R, I, B, and J type instructions, and the structure hazard, control hazard, data hazard, and other three hazards are also successfully solved.