Design and Hardware Realization of 32-Bit Multipliers Based on FPGAs

Abstract

A new approach for optimized multipliers based on the Vedic mathematics principle is introduced. The design aims to meet current Field-Programmable Gate Arrays (FPGAs) requirements. However, the need for high-speed multipliers in Digital Signal Processing (DSP) has become a challenge for researchers to propose and find new multiplier designs that meet the DSP requirement. This paper presents a new 32-bit multiplier suitable for being employed on DSP systems. The multiplier employs the Vedic mathematics principle to produce partial products using fundamental 4x4 multipliers developed by utilizing 6-input LUTs and multiplexers in the same slices yielding a drastic decrease in the area when implemented FPGAs. The use of Carry Ripple/Chain Adder is to get final products. Moreover, the multiplier is developed in a non-pipeline multiplier schema, which is designed without a clock signal in its operation. This structure is the same as combinatorial circuitry. The proposed multiplier has a maximum delay of 14.529 ns, less than other similar multiplier designs.