Design and Functional Verification of Reversible Logic Based FFT Using OHRNS

Abstract

This work shows importance of reversible logic circuits using One-Hot Residue Number System (OHRNS) for arithmetic circuit designing and signal processing (digital) for less delay and less power dissipation applications. OHRNS technique highlight is delay of one active (high) transistor which is equal to the implementation delay which shows better results in comparison to reversible logic design circuits and conventional methods. Another benefit of using OHR is lucidity of implementation when compared to reversible logic circuits and conventional methods. The advantage of using reversible logic design circuits is having minimal power dissipation. Design of arithmetic blocks adder and subtractor using one-hot encoding technique is focused mainly. Frequently these subsystems are used in the design of filters. In this work, the above subsystems implemented using OHR are utilized in designing of FFT computational blocks. The essential blocks required in designing a fast Fourier transform computation block using conventional, OHRNS, reversible logic circuits methods, are implemented in Tanner EDA tool with standard CMOS technology (250 nm), and comparative results are provided. Experimental results show the FFT block implementation using OHRNS technique which dissipates less power, consumes less transistors, and is faster and feasible option in design of efficient circuits when compared to similar implementation techniques such as reversible logic circuits and conventional techniques.