Design and FPGA implementation of efficient integer arithmetic algorithms

Abstract

The design and implementation of various integer arithmetic algorithms are presented. The design process and the various criteria involved in the building of an efficient O(N) 32-bit bit stream-systolic multiplier chip from the algorithmic level to the final implementation stage are described. An entirely different approach is used to implement integer division using the Chinese remaindering theorem. This algorithm generates the first N significant bits of the reciprocal of a number in O(log N) bit steps. This algorithm is asymptotically faster than the implementations currently available for integer division. The scheme is attractive as it forms a basis for the implementation of some more arithmetic functions, like the generation of a power series and multiplication of N N-bit operands in O(log N) time steps. The evaluation and implementation of the modulus function are considered. >