Design and FPGA Implementation of a 2nd Order Adaptive Delta Sigma Modulator with One Bit Quantization

Abstract

This paper presents the design and FPGA implementation of a 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">nd</sup> order all-digital Adaptive Delta Sigma (ΔΣ) modulator with one bit quantization. It has a modulator stage and an adaptation stage. The adaptation stage produces a feedback signal that tracks the input signal and is subtracted from it. This difference signal is in a controlled and reduced range. It is given to the input of the modulator stage which has a 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">nd</sup> order ΔΣ modulator. This results in a reduction of quantization noise and an increase in the overall Signal to Quantization Noise Ratio (SQNR) of the modulator. The design was implemented on a Xilinx Spartan family FPGA using the Xilinx System Generator for DSP tool. The Hardware Co-Simulation mode of the System Generator was used which enables Simulink to run the FPGA directly, thus facilitating extensive testing. The spectral and SQNR analysis of the FPGA output was performed in MATLAB. The 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">nd</sup> order adaptive ΔΣ modulator presented here, exhibits an average SQNR improvement of 24.66 dB, 22.11 dB, 16.59 dB and 8.24 dB over the 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">nd</sup> order non-adaptive ΔΣ modulator at Over Sampling Ratios (OSRs) of 512, 256, 128 and 64 respectively in an input power range of -80 to 20 dB. It also exhibits an increased dynamic range of approximately 24 dB over the 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">nd</sup> order non-adaptive ΔΣ modulator.