Design and fabrication of large capacity bubble memory devices (invited)

Abstract

In order for the magnetic bubble device technology to remain competitive with other memories higher densities are required. Our approach consists of reducing the period of the conventional permalloy devices from the 12-16μm range to the 6-8μm period range. This density allows the fabrication of a 1Mbit chip in a 1cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> area. One of the major obstacles in reducing the NiFe period in the past has been the problem of step coverage. We have developed a NiFe design which is totally planar in processing and which is capable of performing generation, swap, replication and detection. The process consists of a tri-layer deposition of AlCu/SiO <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> /NiFe and then top down masking and material removal steps in which the NiFe is ion milled and the SiO <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> and AlCu are plasma etched. The second level has been designed in such a manner that the NiFe layer provides an aid for alignment and masking for the AlCu process since the NiFe is an excellent mask for the plasma etches. In addition, the patterns are direct slice stepped from a 10X E-Beam reticle which produces minimum features of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">\sim1\mu</tex> m and registration to better than ±¼μm. Several 1Mbit architectural organizations such as 1×1Mbit, 2×512Kbit and 4×256Kbit will be compared from a performance point of view.