Design and Experimentation of Inductorless Low-Pass NGD Integrated Circuit in 180-nm CMOS Technology

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This article introduces an innovative design of a low-pass (LP) negative group delay (NGD) integrated circuit (IC) in the 180-nm CMOS technology. The LP-NGD circuit is an inductorless topology constituted by RC-network with CMOS metal-insulator-metal (MIM) capacitor and polygate resistor. The design methodology is illustrated by considering the chip layout process. Then, the first run simulation is performed with the design rule check (DRC) and 2.5 mm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${\times }$ </tex-math></inline-formula> 2.2 mm layout versus schematic (LVS) approaches. The feasibility of the CMOS LP-NGD IC circuit implementation is validated with chip-onboard (CoB). The proof of concept (PoC) of the LP-NGD miniaturized circuit was tested in both S-parameter and time domain (TD). As expected, the calculated, simulated, and experimented results of CoB showing NGD of about −10 ns over 12 MHz and −10 dB attenuation are confirmed. The active CMOS LP-NGD technology compensates the insertion loss to 2.4 dB, the GD reaches −11 ns, and the reflection loss reaches −20 dB. Moreover, TD investigations were also performed to show the feasibility of generating pulse and arbitrary waveform signal time advance through the designed and fabricated LP-NGD CoB prototypes.