Design and evaluation of shared buffer based NoC

Abstract

New tendencies envisage multiprocessor systems-on-chips (MPSoCs) as a promising solution for high performance embedded System. And the key challenge is how to improve the communication efficiency. Network on Chip (NoC) has been considered as a new paradigm in the next generation communication architecture for its scalability and power efficiency. A NoC prototype which consists of 8 ARM compatible cores and a router-based on-chip network was designed and implemented on FPGA device. An application of JPEG decoding was fulfilled on this prototype and the task partition was discussed. Specially, a method of buffer sharing was proposed. Based on the method, buffer elements can be shared in part between different channels of the router. A well-designed on-chip monitoring network was implemented for Performance evaluation. Experiment results show that the buffer sharing method can save memory resource distinctly.