Abstract
The current monolithic integrated circuits revolution has been growing over past few decades, but the VLSI industry faces problems in the domain of short channel effect, device density, and scaling...
Highlights
Concept regarding deep-sub-micron in CMOS has faced a challenge due to further scaling
As reversible logic synthesis technology has been progressed in the digital logic circuit scenario, recovered outputs form inputs have been employed to facilitate of no loss of information (Misra, Sen, & Wairya, 2017)
We present a novel XOR gate, which is used for designing the reversible Feynman gate
Summary
Concept regarding deep-sub-micron in CMOS has faced a challenge due to further scaling. A new parity-preserving reversible universal QCA gate termed as the PRUG is proposed It is a 3 × 3 gate that realizes three different functionalities at its three primary outputs. Reversible odd parity checker correctly classified cell count of 130, area of 0.143 μm, and nine majority voter gates The limitation of these designs is the more cell count involved in the QCA architecture. It indicates there is an improvement of 36% in Cell count and 42% in the area compared to previous best design (Roohi et al, 2016).
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