Abstract
CAD tool designers have given priority to providing features that will let circuit and logic designers use this custom-memory formal verification and analysis tool without a steep learning curve. This article discusses a few fundamental design decisions behind the successful deployment of a second-generation formal custom-memory equivalence-checking tool, Versys2, in the PowerPC design flows. The Versys2 symbolic simulator was developed at Motorola for verifying equivalence between register-transfer-level (RTL) designs and custom transistor circuit schematics.
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