Design and Demonstration of 820-GHz Array Using Diode-Connected NMOS Transistors in 130-nm CMOS for Active Imaging

Abstract

An 820-GHz 8 $\,\times\,$ 8 diode-connected NMOS transistor active imaging array with an on-chip pixel selection circuit was demonstrated in a 130-nm CMOS technology. The noise performance of this architecture is comparable to the state-of-the-art MOSFET and Schottky diode detector arrays. The imaging array consists of a row and column selector, an array of diode-connected NMOS transistor passive pixels, an analog multiplexer, and a low-noise amplifier bank. At 823 GHz, it achieves 2.56 kV/W of measured mean responsivity with a standard deviation of 18% and 36.2 $\hbox{pW/Hz}^{1/2}$ of measured mean noise equivalent power (NEP) at 1-MHz modulation frequency with a standard deviation of 67%. The mean responsivity is greater than $\sim \hbox{2 kV/W}$ between 815 to 835 GHz. The minimum NEP of 12.6 $\hbox{pW/Hz}^{1/2}$ is the lowest for CMOS based detectors at $\sim \hbox{1 THz}$ . The 8 $\,\times\,$ 8 imaging array occupies 2.0 $\,\times\,$ 1.7 $\hbox{mm}^{2}$ and consumes 9.6 mW of power. Reducing device sizes to support the increase of operating frequency is expected to increase the variability and mitigation approaches will be required. The measured access time for the pixel is $\sim \hbox{40 nS}$ . The number of elements that can be connected in a row is determined by the modulation frequency and can be more than 1000 elements while supporting a frame rate greater than 1000 per second. Lastly, the expressions of responsivity and NEP including $1/{\rm f}$ noise that can be used for the detector optimization are derived and presented .