Design and Defect Analysis of Novel NAND/NOR Gate in Quantum-dot Cellular Automata

Abstract

Quantum-dot Cellular automata is an emerging post-CMOS technology which offers promising features such as high speed, high packaging density and low power. It has led to the emergence of several circuit designs in Quantum-dot Cellular Automata. Circuits are designed in Quantum-dot Cellular Automata using majority gate and inverter. The majority gates function either as an AND or OR gate. NAND/NOR function is implemented by combing AND/OR gate with an inverter. A dedicated NAND/NOR gate will help to develop the QCA layout generation. Few structures are already existing in literature to implement NAND/NOR operation. All the existing designs require large area for implementation. In this paper, a novel NAND/NOR gate is proposed with the same cell count and area of a AND/OR gate. To validate the proposed gate, multiplexer and D-Flip Flop circuits are designed and implemented using the proposed gate. The simulation results show that the proposed gate consumes less area than the existing state-of-the-art designs. Defect analysis is performed for the proposed gate and compared with the existing designs. All the simulations and verifications are done using QCADesigner.