Design and Construction of a Low Cost All-Digital Phase Locked Loop Based on Field Programmable Gate Array

Abstract

The phase-locked loop (PLL) is a key element to capture the voltage phase of the grid in power systems with high permeability of new energy sources. An accurate phase information catcher which can be applied in the field can provide a strong support for the control process of the system. This paper constructs a low-cost all-digital PLL (ADPLL) on an embedded field-programmable gate array (FPGA) for real-time (RT) digital simulation. Compared with offline simulation, RT digital simulation can realize hardware-in-loop (HIL) testing of utility connected devices to validate their performance in every working condition, which would not be possible using only experimental tests. Meanwhile, an improved simulation architecture construction method based on Algorithm Architecture Adequation (A-A-A) is presented in this paper. This method further saves the internal hardware resources on the basis of making full use of the parallel computing capability of FPGA. Analysis and experimental results made based on an FPGA ALTERA Stratix V show that the proposed modeling algorithm can achieve both efficiency and accuracy.