Abstract
Nanomagnet Logic (NML) is a device architecture that utilizes the magnetization of nano-scale magnets to perform logical operations. NML has been experimentally demonstrated and operates at room temperature. Because the nanomagnets are non-volatile, as data flows through a circuit, it is inherently pipelined. This feature makes NML an excellent fit for systolic architectures, which could enable low-power, high-throughput systems that can address a variety of application-level tasks. When considering possible NML systolic systems, the underlying systolic clocking scheme affects both architectural design and performance. In this paper we explore these issues in the context of two NML designs for convolution. One design is based on a 3-phase clocking scheme and uni-directional dataflow, and another is based on a 2-phase clocking scheme and bi-directional dataflow. We compare the two NML systolic designs in terms of area, delay, and energy. We also compare the NML and CMOS implementations of the design in terms of energy and delay. Results are supported by physical level simulation.
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